The present invention relates generally to a method for removing a hard mask on an SOI substrate without using a chemical mechanical polish (CMP) process.
For embedded DRAM (eDRAM) processing in 22 nm technology and beyond, a conventional spacer at a sidewall of a deep trench cannot be used to etch the deep trench sufficiently. Without the spacer at the sidewall of the deep trench, it is difficult to remove a hard mask material. When etching a deep trench in an SOI substrate, it is difficult to remove the hard mask material due to the presence of a BOX layer. Conventional methods of hard mask removal on bulk substrates use a wet process. Borosilicate glass (BSG) is typically used as the hard mask material. BSG can be easily etched by a wet process, such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF). Since the SOI substrate has the BOX layer, the wet process cannot be used. A CMP process may be used to remove the hard mask material. However, the CMP process results in hard mask thickness variation because of variation in the CMP process itself and hard mask material thickness non-uniformity. CMP process non-uniformity causes recess depth variation directly and may result in deep trench to substrate leakage current. It may also cause a deep trench to deep trench short or an exposed node dielectric by the etching process. The exposed node dielectric may result in substrate warpage by oxidation of a metal high-dielectric constant (MHK) node electrode. A two step deep trench CMP process may reduce the depth variation, but also increases cost.